附录B：程序源代码
#include <msp430f5529.h>
#include"UCS.h"
#include"DELAY.h"
#define HSTT 12
#define VSTT 45
#define HU 1
#define VU 10
unsigned int paths=0;
#define inversion P6OUT^=BIT1
void trigger_init()
{
P1DIR &=~BIT5; //P1.5行同步信号
P1REN |= BIT5;
P1OUT |= BIT5;
P1IES |= BIT5;//下降沿触发
P1IE |= BIT5;
P2DIR&=~BIT2;//P2.2场同步信号
P2REN|=BIT2;
P2OUT|=BIT2;
P2IES|=BIT2;
P2IE|=BIT2;
P6DIR|= BIT0+BIT1;
P6OUT&= ~BIT0; //P6.0正脉冲信号，控制字符信号
P6OUT|=BIT1; //P6.1负脉冲信号，控制视频信号
}
void main(void)
{
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
_DINT();
INTTIME();
trigger_init();
__bis_SR_register(LPM1_bits+GIE);
}
#pragma vector=PORT1_VECTOR
__interrupt void Port_1(void)
{
paths++;
if((paths>=VSTT)&(paths<=VSTT+VU))
{
delay_us(HSTT+HU);
inversion;
delay_us(3*HU);
inversion;
}
else if((paths>VSTT+VU)&(paths<=VSTT+2*VU))
{
delay_us(HSTT-0.5);
inversion;
delay_us(HU);
inversion;
delay_us(3*HU);
inversion;
delay_us(HU);
inversion;
}
else if((paths>VSTT+2*VU)&(paths<=VSTT+7*VU))
{
delay_us(HSTT-1);
inversion;
delay_us(HU);
inversion;
}
else if((paths>VSTT+7*VU)&(paths<=VSTT+8*VU))
{
delay_us(HSTT-1.5);
inversion;
delay_us(HU);
inversion;
delay_us(3*HU);
inversion;
delay_us(HU);
inversion;
}
else if((paths>VSTT+8*VU)&(paths<=VSTT+9*VU))
{
delay_us(HSTT-2+HU);
inversion;
delay_us(3*HU);
inversion;
}
P1IFG&= ~BIT5;
}
#pragma vector=PORT2_VECTOR
__interrupt void Port_2(void)
{
paths=0;
P2IFG&=~BIT2;
}
/*
* UCS.C
*
*/
#include<msp430f5529.h>
#include"UCS.h"
void SetVcoreUp (unsigned int level)
{
// Open PMM registers for write
PMMCTL0_H = PMMPW_H;
// Set SVS/SVM high side new level
SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
// Set SVM low side to new level
SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
// Wait till SVM is settled
while ((PMMIFG & SVSMLDLYIFG) == 0);
// Clear already set flags
PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);
// Set VCore to new level
PMMCTL0_L = PMMCOREV0 * level;
// Wait till new level reached
if ((PMMIFG & SVMLIFG))
while ((PMMIFG & SVMLVLRIFG) == 0);
// Set SVS/SVM low side to new level
SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
// Lock PMM registers for write access
PMMCTL0_H = 0x00;
}
void INTTIME(void)
{
SetVcoreUp (0x01);
SetVcoreUp (0x02);
SetVcoreUp (0x03);
UCSCTL3 = SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_2; // Set ACLK = REFO
__bis_SR_register(SCG0); // Disable the FLL control loop
// Disable the FLL control loop
UCSCTL0 = DCO1+DCO2+ DCO3+ DCO4;
UCSCTL1 = DCORSEL_4; // Select DCO range 50MHz operation
UCSCTL2 = FLLD_0 +487;
// (N + 1) * FLLRef = Fdco
__bic_SR_register(SCG0);
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 25 MHz / 32,768 Hz ~ 780k MCLK cycles for DCO to settle
__delay_cycles(782000);
// Loop until XT1,XT2 & DCO stabilizes - In this case only DCO has to stabilize
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG);
}
